A programmable resistive device is generally referred to a device's resistance states that may change after means of programming. Resistance states can also be determined by resistance values. For example, a resistive device can be a One-Time Programmable (OTP) device, such as electrical fuse, and the programming means can apply a high voltage to induce a high current to flow through the OTP element. When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, or burned into a high or low resistance state (depending on either fuse or anti-fuse). A programmable resistive device can be programmed reversibly and repetitively based on the magnitude, duration, or voltage/current limit of the current flowing through the programmable resistive element, such as the films and electrodes in PCRAM (Phase-Change RAM), RRAM (Resistive RAM), CBRAM (Conductive Bridge RAM). A programmable resistive device can also be programmed based on the direction of the current flowing through the programmable resistive element, such as MTJ (Magnetic Tunnel Junction) in MRAM, or resistive films in some kinds of RRAM or CBRAM.
An electrical fuse is a common OTP which is a programmable resistive device that can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combination thereof. The metal can be aluminum, copper, or other transition metals. One of the most commonly used electrical fuses is a CMOS gate, fabricated in silicided polysilicon, used as interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The electrical fuse can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator.
A conventional programmable resistive memory cell 10 using MOS as program selector is shown in FIG. 1(a). The cell 10 consists of a resistive element 11 and an NMOS program selector 12. The resistive element 11 is coupled to the drain of the NMOS 12 at one end, and to a high voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a low voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the resistive cell 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One of the most common resistive elements is a silicided polysilicon, the same material and fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps for a fuse with width of 40 nm to about 20 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The resistive memory cell 10 can be organized as a two-dimensional array with all select signals Sel's and voltages V−'s in a row coupled as wordlines (WLs) and a ground line, respectively, and all voltages V+'s in a column coupled as bitlines (BLs).
Another programmable resistive device using diode as program selector is shown in FIG. 1(b). The programmable resistive device 15 has a programmable resistive element 16 and a diode 17 as program selector. The programmable resistive element 16 is coupled between an anode of the diode 17 and a high voltage V+. A cathode of the diode 17 is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the programmable resistive element 16 can be programmed into high or low resistance states, depending on magnitude, duration, current/voltage limit, current direction, or combinations thereof. The programmable resistive cell 15 can be organized as a two dimensional array with all voltages V−'s in a row coupled as wordline bars (WLBs), and all voltages V+'s in a column coupled as bitlines (BLs).
A FinFET device is a 3D type of MOS device, instead of a planar CMOS, suitable for CMOS generations beyond 20 nm. FIG. 2(a) shows a conventional planar CMOS with source, drain, and channel laid on the silicon surface and a MOS gate built on top of the silicon substrate. FIG. 2(b) shows a 3D conceptual view of a MOS in a FinFET bulk technology. A tall and thin silicon island can be built on a substrate. The two sides and top surface of the island are grown with gate oxide and then a MOS gate can be built across the thin island to divide the fin into source, drain, and body. The channel region can be extended into the body because the fin is so thin such that the body is almost depleted. After the gate is built, the surface is oxidized to provide isolation between different fins. The current still flows in parallel to the silicon surface, but the channel width is twice of the fin height plus the fin thickness. FIG. 2(c) shows a 3D conceptual view of a MOS in a FinFET SOI technology. The FinFET SOI is very similar to the FinFET bulk except that the tall and thin fins in the FinFET SOI are isolated from the silicon substrate. A FinFET can have multiple fins, just like a planar MOS can have multiple fingers. The sources or drains of the multiple fins can be coupled together by constructing extended source/drain regions. The extended S/D regions can be built on field oxide after the fins and gates are fabricated, and therefore, is thermally isolated from the substrate. The extended source/drain can connect multiple fins together or one fin each. The extended S/D can be fabricated by depositing or growing polysilicon, polycrystalline Si/SiGe, lateral epitaxial silicion/SiGe, or Selective Epitaxial Growth (SEG), etc. The extended source/drain can be a diamond shape with facets and rise above the fin height when doping with SiGe in certain crystal directions, especially for source/drain of a PMOS. FIG. 2(d) shows another 3D conceptual view of a multiple-fin FinFET. FIG. 2(e) shows a SEM photo of a multi-fin FinFETs with sources/drains coupled by extended sources/drains.
FIG. 2(f) shows another 3D view of a FinFET with more structure details as an example. The FinFET is a tall and narrow structure of fin built on a substrate. Then, a layer of field oxide is deposited or grown on a substrate. A MOS gate is fabricated across the fin to divide the fin into source and drain regions. The two ends of the source and drain regions are grown with epitaxial to provide more area for contacts.
FIGS. 2(fa) and 2(fb) show cross sections of three (3) different planes, corresponding to the FIG. 2(f), The MOS device is built like in the conventional planar MOS with STI (Shallow Trench Isolation), gate oxide, gate, gate spacer, LDD (Lightly Doped Drain) and epitaxial source/drain. As an example, the gate length can be 22 nm, fin width can be 11 nm. Fin height can be 55 nm, STI thickness is 100 nm, shallow LDD junction is 5 nm, and space between gate and epitaxial S/D is 30 nm, referring to Tsunaki Takahashi, et al, “Thermal-Aware Device Design of Nanoscale Bulk/SOI FinFETs: Suppression of Operation Temperature and Its Variability,” IEEE IEDM, December, 2011, pp. 809-812.
FIG. 3(a1) shows a top view of a 4-fin FinFET 20, loosely corresponding to the 3D views of FIGS. 2(b), 2(c), 2(d), and 2(e). The FinFET 20 has 4 fins, 21-1 to 21-4, on a substrate. The fins are crossed by a gate 22 in a perpendicular direction. Extended source and drain, 27 and 23, respectively, are built to connect the sources and drains of each fin together. Extended source/drain or active region 26 is used as a body tie for bulk FinFET. Two contact holes 29 per fin allow sources or drains of the FinFET being coupled to metal interconnect (not shown). In some embodiments, the contacts can be replaced by metal-0, i.e. an local interconnect that can provide self-align and low contact resistance. The FinFET 20 can be covered by an N+ implant layer 24 for a NMOS FinFET. The body tie 26 can be covered by a P+ implant 25. FIG. 3(a2) shows an equivalent circuit 20′ of FIG. 3(a1) that has 4 transistors 21′-1 to 21′-4 corresponding to 4 FinFETs in FIG. 3(a1).
As a reference FinFET device in a 45 nm technology, the parameters of the FinFET shown in FIG. 3(a1) can be: fin width Wfin=10 nm, gate length Lg=45 nm, fin-to-fin space S=200 nm, source/drain distance Ls=Ld=90 nm, contact size=20×20 nm, and fin height H=50 nm. Refer to A. Griffoni et al, “Next Generation Bulk FinFET Devices and Their Benefits for ESD Robustness,” IEEE EOS/ESD Sym., 2009, 09-59.
A FinFET is 3D structure that has many properties a planar MOS device cannot have. Other than distinct electrical properties from the planar MOS, the tall and narrow silicon islands erected from a substrate have poor thermal conductivity.